Processed semiconductor wafers typically comprise an array of substantially isolated integrated circuitry locations, which are subsequently separated to form semiconductor dies (or chips). In order to test the operability of the integrated circuitry of a die location on a wafer, a wafer probe card is applied to each die location. The wafer probe card includes a series of probe pins that are placed in electrical connection with a die location's bonding pads, which in turn connect to the die location's circuitry. The probe pins apply voltages to the input bonding pads and measure the resulting output electrical signals from the output bonding pads. After testing, the individual semiconductor dies are separated from one another, followed by packaging with bonding or connecting bonding wires to the respective bonding pads. If the wafer probe card's pins are in physical contact with the respective bonding pads, the bonding pads will be subject to scratches that may deteriorate the reliability of bonding/connection between each bonding pad and bonding wire. Therefore, the so-called probe pads are provided as accessible redundant contact pads electrically coupled to the bonding pads.
An additional hardware limitation relevant to testing the die locations is the spacing between the probe pins of the wafer probe card. Specifically, the probe pins may be spaced further apart than the bonding pads in a particular area of a die location. As a result, one bonding pad in that area may not be serviceable by a probe pin. As a solution, prior art teaches providing a probe pad in another area of the die location that can be reached by a probe pin. This redundant probe pad is connected to the same logic circuit as the unserviceable bonding pad.
There may also be other reasons for including additional probe pads on a die. Regardless of the reasons, prior art allows these redundant probe pads to remain connected to the logic circuit after they are no longer needed. By remaining connected, these redundant probe pads contribute additional capacitance to their associated logic circuits and thereby degrade performance of the die.